Conventionally, various types of circuit substrates (e.g. printed circuit boards) have been installed in radio communication devices and electronic devices (e.g. cellular phones, personal computers having wireless communication functions, and handheld information terminals). However, electronic devices in which semiconductor devices and integrated circuits are mounted on circuit substrates suffer from problems in that electromagnetic waves of parts may cause electromagnetic noise to influence other parts, resulting in occurrence of erroneous operations. As noise propagation paths, power distribution systems may propagate noise to influence electronic circuits, or noise may directly influence signal lines.
A noise-generating structure owing to a power distribution system will be described.
FIG. 12 is a perspective view of a circuit substrate 101 mounting a plurality of integrated circuits (LSI circuits) 102 to 105 thereon. As high-speed signal transmission paths, signal lines 106 and 107 are wired between integrated circuits 102 and 103 and between integrated circuits 104 and 105. Additionally, a plurality of bypass capacitors 108 is mounted on the circuit substrate 101. A ground plane GND is formed around these parts on the surface of the circuit substrate 101. A power plane (not shown) is formed as an internal layer inside the circuit substrate 101. A power source 109 is mounted on the circuit substrate 101 and connected to the power plane and the ground plane GND.
Next, the operation of the circuit substrate 101 shown in FIG. 12 will be described.
FIG. 13 is an equivalent circuit of the circuit substrate 101 precluding the bypass capacitor 108. In FIG. 13, due to switching on/off of transistors (not shown) caused by a signal flowing from the integrated circuit 102 to the integrated circuit 103, a charging/discharging current I may flow from the power source 109 to the power terminal or the ground plane GND. At this time, a voltage drop may occur due to parasitic inductance of the power plane or the ground plane GND at a position between the integrated circuits 102 and 104; hence, a source voltage is correspondingly reduced to exert an influence of power noise N on the integrated circuit 104.
To suppress the above voltage drop, it is necessary to mount the bypass capacitor 108 in proximity to the integrated circuits 102 to 105.
FIG. 14 is an equivalent circuit of the circuit substrate 101 mounting the bypass capacitor 108 thereon. Herein, the capacitor 108 is connected between the power terminal and the ground terminal with respect to each of the integrated circuits 102 to 105. In this circuit configuration, for example, when a signal flows from the integrated circuit 102 to the integrated circuit 103, a charging/discharging current I is supplied to the bypass capacitor 108, positioned proximate to the integrated circuit 102, through a path shown by a dashed line. For this reason, a high-frequency current may not flow outside the loop configured of the integrated circuit 102 and the bypass capacitor 108; hence, it is possible to reduce an influence of the charging/discharging current I exerted on the other integrated circuits 103 to 105.
Next, the structure in which noise directly influences signal lines will be described.
FIG. 15 is a perspective view of the circuit substrate 101 mounting a plurality of integrated circuits 102 to 105 thereon. As high-speed signal transmission paths, the signal lines 106 and 107 are wired between the integrated circuits 102 and 103 and between the integrated circuits 104 and 105. The signal line 106 causing an electromagnetic field due to a signal transmitted therethrough may be electromagnetically coupled with the signal line 107 by way of the surrounding space and the circuit substrate 101. For this reason, an electromagnetic influence of the signal line 106 may be superimposed on a signal S1 as noise N, thus causing a degraded signal S2 to be transmitted to the integrated circuit 105.
For this reason, it is necessary to insert a filter into a signal line so as to eliminate noise N coupled with the signal line. In FIG. 15, a plurality of chip inductors 109 is serially inserted into the signal line 107 while a chip capacitor 110 is inserted in parallel, thus forming a T-shape filter. The T-shape filter serves as a low-pass filter (LPF) which is able to eliminate high-frequency noise.
FIGS. 16(a) to (e) show configurations of LPFs using inductors and capacitors. FIG. 16(a) shows an LPF in which an inductor 120 is serially connected to a signal line. FIG. 16(b) shows an LPF in which a capacitor 130 is inserted between a signal line and ground in parallel. FIG. 16(c) shows an L-shaped LPF in which an inductor 121 is serially connected to a signal line while a capacitor 131 is inserted between a signal line and ground in parallel. FIG. 16(d) shows a T-shaped LPF which is configured of inductors 122, 123 and a capacitor 132. FIG. 16(e) shows a π-shaped LPF which is configured of an inductor 124 and capacitors 133, 134. The above LPF is inserted into a dotted block 140 positioned between the integrated circuits 104 and 105 in an equivalent circuit shown in FIG. 17 (i.e. an equivalent circuit for the integrated circuits 104 and 105 shown in FIG. 15), thus eliminating high-frequency noise coupled with a signal line.
Other than the noise suppression structure for mounting inductors and capacitors on the circuit substrate 101, a variety of noise suppression structures has been proposed. For example, Patent Literature 1 discloses a noise suppression structure for multilayered printed circuit boards. In this noise suppression structure, a first conductor transmitting a high-frequency current therethrough is electromagnetically coupled with a noise suppression layer through an insulating layer, while the noise suppression layer is electromagnetically coupled with a second conductor through the insulating layer.
Patent Literature 2 discloses a noise reduction method in a circuit substrate. Herein, high-frequency noise, caused by an integrated circuit (IC), flows from an IC ground terminal to a first via-hole by way of an IC ground pattern formed in a surface wiring layer; it flows from the first via-hole to a first ground pattern; it flows from the first ground pattern to a third ground pattern, which is formed in a base wiring layer, by way of a second via-hole; it flows from the third ground pattern by way of a third via-hole and a second ground pattern, and then it is discharged into the external space.
Patent Literature 3 discloses a memory module for suppressing noise emission. Herein, a multilayered printed circuit board includes a plurality of signal lines or a power pattern as well as a surrounding ground pattern, which is connected through a connecting via. Additionally, a plane antenna configured of a surrounding ground pattern causes an electric field in an opposite direction so as to suppress noise emission from a multilayered printed circuit board.